1. Field of the Invention
The present invention relates to a dynamic type semiconductor memory device employing one-transistor type dynamic memory cells composed of a storage capacitor and a gating MOS transistor and, more particularly to an improvement of a structure of the storage capacitor of the memory cell.
2. Description of the Related Art
In memory technology, the emphasis has been made on increasing the memory capacity i.e., the integration density of memory cells in a single semiconductor chip. To this end, it is important to minimize the surface area of the respective memory cells because the surface area of the chip usable for a memory cell array is limited. Under the above circumstance, the one-transistor type memory cell composed of a storage capacitor and a gating transistor is advantageously utilized in the dynamic memory device with its minimized occupation area. In this memory device employing the one-transistor type memory cells, a capacitance value of the storage capacitor is a very important factor to determine a read-write characteristic of the memory device, because data stored in the storage capacitor is read out in accordance with a capacitance ratio between the storage capacitor and a stray capacitance of a bit line. Particularly, for a high signal-to-noise ratio, it is required that the capacitance of the storage capacitor should be large compared to the stray capacitance of the bit line. In order to provide the storage capacitor having a large capacitance, the so-called stack-type capacitor and the trench-type capacitor have been known.
The stack-type capacitor is constructed in such a manner that a pair of capacitor plates with a dielectric insulating layer are formed above a major surface of a semiconductor chip to overlay the gate of the gating transistor of the memory cell and a part of a word line. Namely, according to the stack-type capacitor structure, the storage capacitor is partially overlapped with the gating transistor so that a resultant surface area occupied by such large capacitance storage capacitor and the gating transistor can greatly reduced.
The, the trench-type capacitor is formed in such a manner that a groove or trench is formed in a major surface of the semiconductor chip and an upper capacitor plate is formed in the trench along its surface via an insulating layer. According to the trench-type capacitor, an effective surface of the capacitor plate is increased in a vertical direction along the depth of trench so that the storage capacitor having a relatively large capacitance is obtained with a small surface area on the semiconductor chip.
However, the conventional capacitor techniques stated above have many shortcomings. In regard to the stack-type capacitor, first, the surface area is not increased so much in comparison with that of the conventional planar-type capacitor since the stepped part formed over the gate electrode, the word line or the like is small. To increase the capacitance, it is necessary to increase an area occupied by a memory cell. In regard to the trench type capacitor, wherein the trench is formed in the semiconductor substrate, the capacitance can be increased by forming the trench deeper without enlarging the memory cell. However, this capacitor has short-comings that the leakage of stored charge increases with the depth of the trench and that adjacent trenches must be separated sufficiently to prevent the mutual contact of depletion layers expanding from these trenches, so as not to cause a leakage between the trenches.